Espressif Systems /ESP32-S2 /UHCI0 /INT_CLR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INT_CLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RX_START_INT_CLR)RX_START_INT_CLR 0 (TX_START_INT_CLR)TX_START_INT_CLR 0 (RX_HUNG_INT_CLR)RX_HUNG_INT_CLR 0 (TX_HUNG_INT_CLR)TX_HUNG_INT_CLR 0 (IN_DONE_INT_CLR)IN_DONE_INT_CLR 0 (IN_SUC_EOF_INT_CLR)IN_SUC_EOF_INT_CLR 0 (IN_ERR_EOF_INT_CLR)IN_ERR_EOF_INT_CLR 0 (OUT_DONE_INT_CLR)OUT_DONE_INT_CLR 0 (OUT_EOF_INT_CLR)OUT_EOF_INT_CLR 0 (IN_DSCR_ERR_INT_CLR)IN_DSCR_ERR_INT_CLR 0 (OUT_DSCR_ERR_INT_CLR)OUT_DSCR_ERR_INT_CLR 0 (IN_DSCR_EMPTY_INT_CLR)IN_DSCR_EMPTY_INT_CLR 0 (OUTLINK_EOF_ERR_INT_CLR)OUTLINK_EOF_ERR_INT_CLR 0 (OUT_TOTAL_EOF_INT_CLR)OUT_TOTAL_EOF_INT_CLR 0 (SEND_S_REG_Q_INT_CLR)SEND_S_REG_Q_INT_CLR 0 (SEND_A_REG_Q_INT_CLR)SEND_A_REG_Q_INT_CLR 0 (DMA_INFIFO_FULL_WM_INT_CLR)DMA_INFIFO_FULL_WM_INT_CLR

Description

Interrupt clear bits

Fields

RX_START_INT_CLR

Set this bit to clear UHCI_RX_START_INT interrupt.

TX_START_INT_CLR

Set this bit to clear UHCI_TX_START_INT interrupt.

RX_HUNG_INT_CLR

Set this bit to clear UHCI_RX_HUNG_INT interrupt.

TX_HUNG_INT_CLR

Set this bit to clear UHCI_TX_HUNG_INT interrupt.

IN_DONE_INT_CLR

Set this bit to clear UHCI_IN_DONE_INT interrupt.

IN_SUC_EOF_INT_CLR

Set this bit to clear UHCI_IN_SUC_EOF_INT interrupt.

IN_ERR_EOF_INT_CLR

Set this bit to clear UHCI_IN_ERR_EOF_INT interrupt.

OUT_DONE_INT_CLR

Set this bit to clear UHCI_OUT_DONE_INT interrupt.

OUT_EOF_INT_CLR

Set this bit to clear UHCI_OUT_EOF_INT interrupt.

IN_DSCR_ERR_INT_CLR

Set this bit to clear UHCI_IN_DSCR_ERR_INT interrupt.

OUT_DSCR_ERR_INT_CLR

Set this bit to clear UHCI_OUT_DSCR_ERR_INT interrupt.

IN_DSCR_EMPTY_INT_CLR

Set this bit to clear UHCI_IN_DSCR_EMPTY_INT interrupt.

OUTLINK_EOF_ERR_INT_CLR

Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt.

OUT_TOTAL_EOF_INT_CLR

Set this bit to clear UHCI_OUT_TOTAL_EOF_INT interrupt.

SEND_S_REG_Q_INT_CLR

Set this bit to clear UHCI_SEND_S_REG_Q_INT interrupt.

SEND_A_REG_Q_INT_CLR

Set this bit to clear UHCI_SEND_A_REG_Q_INT interrupt.

DMA_INFIFO_FULL_WM_INT_CLR

Set this bit to clear UHCI_DMA_INFIFO_FULL_WM_INT interrupt.

Links

() ()